View MC33067_5867586.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2005 october, 2005 ? rev. 11 1 publication order number: mc34067/d mc34067, MC33067 high performance resonant mode controllers the mc34067/MC33067 are high performance zero voltage switch resonant mode controllers designed for off?line and dc?to?dc converter applications that utilize frequency modulated constant off?time or constant deadtime control. these integrated circuits feature a variable frequency oscillator, a precise retriggerable one?shot timer, temperature compensated reference, high gain wide bandwidth error amplifier, steering flip?flop, and dual high current totem pole outputs ideally suited for driving power mosfets. also included are protective features consisting of a high speed fault comparator and latch, programmable soft?start circuitry, input undervoltage lockout with selectable thresholds, and reference undervoltage lockout. these devices are available in dual?in?line and surface mount packages. features ? zero voltage switch resonant mode operation ? variable frequency oscillator with a control range exceeding 1000:1 ? precision one?shot timer for controlled off?time ? internally trimmed bandgap reference ? 4.0 mhz error amplifier ? dual high current totem pole outputs ? selectable undervoltage lockout thresholds with hysteresis ? enable input ? programmable soft?start circuitry ? low startup current for off?line operation ? pb?free packages are available* figure 1. simplified block diagram noninverting input 11 8 6 16 3 2 1 osc charge enable / uvlo adjust v cc 15 5 14 12 13 v ref uvlo error amp v cc uvlo / enable fault detector/ latch 2.5 v clamp soft?start one?shot output b inverting input soft?start 7 error amp output one?shot oscillator control current osc rc 9 ground 4 fault input 10 pwr gnd output a v ref variable frequency oscillator steering flip?flop 5.0 v reference *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagrams x = 3 or 4 a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package pdip?16 p suffix case 648 1 16 soic?16w dw suffix case 751g 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pin connections (top view) v ref osc charge osc rc osc control current gnd error amp out inverting input noninverting input one?shot rc v cc drive output b c soft?start enable/uvlo adjust drive output a power gnd fault input http://onsemi.com 16 1 mc3x067dw awlyywwg see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 16 1 mc3x067p awlyywwg 16 1
mc34067, MC33067 http://onsemi.com 2 maximum ratings rating symbol value unit power supply voltage v cc 20 v drive output current, source or sink (note 1) ? continuous ? pulsed (0.5 s, 25% duty cycle i o 0.3 1.5 a error amplifier, fault, one?shot, oscillator and soft?start inputs v in ? 1.0 to + 6.0 v uvlo adjust input v in(uvlo) ? 1.0 to v cc v power dissipation and thermal characteristics dw suffix, plastic package, case 751g t a = 25 c thermal resistance, junction?to?air p suffix, plastic package, case 648 t a = 25 c thermal resistance, junction?to?air p d r ja p d r ja 862 145 1.25 100 mw c/w w c/w operating junction temperature t j + 150 c operating ambient temperature mc34067 MC33067 t a 0 to + 70 ? 40 to + 85 c storage temperature t stg ? 55 to + 150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. ordering information device package shipping ? MC33067dw soic?16w 47 units / rail MC33067dwg soic?16w (pb?free) 47 units / rail MC33067dwr2 soic?16w 1000 / tape & reel MC33067dwr2g soic?16w (pb?free) 1000 / tape & reel MC33067p pdip?16 25 units / rail MC33067pg pdip?16 (pb?free) 25 units / rail mc34067dw soic?16w 47 units / rail mc34067dwg soic?16w (pb?free) 47 units / rail mc34067dwr2 soic?16w 1000 / tape & reel mc34067dwr2g soic?16w (pb?free) 1000 / tape & reel mc34067p pdip?16 25 units / rail mc34067pg pdip?16 (pb?free) 25 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc34067, MC33067 http://onsemi.com 3 electrical characteristics (v cc = 12 v [note 2], r osc = 18.2 k, r vfo = 2940 , c osc = 300 pf, r t = 2370 , c t = 300 pf, c l = 1.0 nf. for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies (note 3), unless otherwise noted.) characteristic symbol min typ max unit reference section reference output voltage (i o = 0 ma, t j = 25 c) v ref 5.0 5.1 5.2 v line regulation (v cc = 10 v to 18 v) reg line ? 1.0 20 mv load regulation (i o = 0 ma to 10 ma) reg load ? 1.0 20 mv total output variation over line, load, and temperature v ref 4.9 ? 5.3 v output short circuit current (0 c to 70 c) (?40 c to 85 c) i o 30 25 100 100 190 225 ma reference undervoltage lockout threshold v th 3.8 4.3 4.8 v error amplifier input offset voltage (v cm = 1.5 v) v io ? 1.0 10 mv input bias current (v cm = 1.5 v) i ib ? 0.2 1.0 a input offset current (v cm = 1.5 v) i io ? 0 0.5 a open loop voltage gain (v cm = 1.5 v, v o = 2.0 v) a vol 70 100 ? db gain bandwidth product (f = 100 khz) t a = 25 c t a = t low to t high gbw 3.0 2.7 5.0 ? ? ? mhz input common mode rejection ratio (v cm = 1.5 v to 5.0 v) cmr 70 95 ? db power supply rejection ratio (v cc = 10 v to 18 v, f = 120 hz) psr 80 100 ? db output voltage swing high state (i source = 2.0 ma) low state (i sink = 4.0 ma) v oh v ol 2.8 ? 3.2 0.6 ? 0.8 v 1. maximum package power dissipation limits must be observed. 2. adjust v cc above the startup threshold voltage before setting to 12 v. 3. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 4. t low =0 c for mc34067 =?40 c for MC33067 t high =+70 c for mc34067 =+85 c for MC33067
mc34067, MC33067 http://onsemi.com 4 electrical characteristics (continued) (v cc = 12 v [note 6], r osc = 18.2 k, r vfo = 2940 , c osc = 300 pf, r t = 2370 , c t = 300 pf, c l = 1.0 nf. for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies (note 7), unless otherwise noted.) characteristic symbol min typ max unit oscillator frequency (error amp output low) total variation (v cc = 10 v to 18 v, t a = t low to t high ) f osc(low) 490 525 550 khz frequency (error amp output high) total variation (v cc = 10 v to 18 v, t a = t low to t high ) f osc(high) 1850 2050 2200 khz oscillator control input voltage, pin 3 v in ? 2.5 ? v one?shot drive output off?time t a = 25 c total variation (v cc = 10 v to 18 v, t a = t low to t high ) t blank 235 225 250 ? 270 280 ns drive outputs output voltage low state (i sink = 20 ma) low state (i sink = 200 ma) high state (i source = 20 ma) high state (i source = 200 ma) v ol v oh ? ? 9.5 9.0 0.8 1.5 10.3 9.7 1.2 2.0 ? ? v output voltage with uvlo activated (v cc = 6.0 v, i sink = 1.0 ma) v ol(uvlo) ? 0.8 1.2 v output voltage rise time (c l = 1.0 nf) t r ? 20 50 ns output voltage fall time (c l = 1.0 nf) t f ? 15 50 ns fault comparator input threshold v th 0.93 1.0 1.07 v input bias current (v pin 10 = 0 v) i ib ? ? 2.0 ?10 a propagation delay to drive outputs (100 mv overdrive) t plh(in/out) ? 60 100 ns soft?start capacitor charge current (v pin 11 = 2.5 v) i chg 4.5 9.0 14 a capacitor discharge current (v pin 11 = 2.5 v) i dischg 3.0 8.0 ? ma undervoltage lockout startup threshold, v cc increasing enable/uvlo adjust pin open enable/uvlo adjust pin connected to v cc v th(uvlo) 14.8 8.0 16 9.0 17.2 10 v minimum operating voltage after turn?on, v cc decreasing enable/uvlo adjust pin open enable/uvlo adjust pin connected to v cc v cc(min) 8.0 7.6 9.0 8.6 10 9.6 v enable/uvlo adjust shutdown threshold voltage v th(enable) 6.0 7.0 ? v enable/uvlo adjust input current (pin 9 = 0 v) i in(enable) ? ? 0.2 ? 1.0 ma total device power supply current (enable/uvlo adjust pin open) startup (v cc = 13.5 v) operating (f osc = 500 khz) (note 6) i cc ? ? 0.5 27 0.8 35 ma 5. maximum package power dissipation limits must be observed. 6. adjust v cc above the startup threshold voltage before setting to 12 v. 7. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 8. t low =0 c for mc34067 =?40 c for MC33067 t high =+70 c for mc34067 =+85 c for MC33067
mc34067, MC33067 http://onsemi.com 5 a vol , open loop voltage gain (db) r t , timing resistor (k ) r osc , oscillator timing resistor (k ) one?shot period is measured at the drive outputs. oscillator discharge time is measured at the drive outputs. f osc c osc = 200 pf 60 30 20 10 6.0 3.0 500 0 , oscillator frequency (khz) t dischg , oscillator discharge time ( s) 3500 3000 2500 2000 1500 1000 i osc , oscillator control current ( a) 0.35 0.30 0.25 0.20 0.15 0.10 i osc , oscillator control current (ma) t os , one?shot period ( s) 0 0.05 200 v cc = 12 v t a = 25 c r osc = 18.2 k 400 300 100 500 c osc = 300 pf 0 ?10 ?20 ?30 ?40 ?50 50 40 30 20 10 0 f, frequency (hz) , reference output voltage change (mv) t a , ambient temperature ( c) ?20 ? ?10 gain v ref 50 60 70 80 90 100 120 110 0, excess phase (degrees) c osc = 500 pf c osc = 300 pf v cc = 12 v r vfo = r t = c t = 500 pf t a = 25 c figure 2. oscillator timing resistor versus discharge time figure 3. oscillator frequency versus oscillator control current figure 4. error amp output low state voltage versus oscillator control current figure 5. one?shot timing resistor versus period figure 6. open loop voltage gain and phase versus frequency figure 7. reference output voltage change versus temperature 0 400 800 1200 1600 2000 0 20406080100 0 0.5 1.0 1.5 2.0 2.5 3.0 0.1 0.3 0.6 1.0 3.0 6.0 10 10 k 100 k 1.0m 10m ?55 ?25 0 25 50 75 125 100 v cc = 12 v v o = 2.0 v r l = 100 k t a = 25 c v cc = 12 v r l = *v ref at t a = 25 c v cc = 12 v c osc = 500 pf r osc = 100 k t a = 25 c phase margin = 64 *v ref = 5.1 v c t = 200 pf c t = 300 pf c t = 500 pf phase *v ref = 5.2 v *v ref = 5.0 v v ol , output low state voltage (v)
mc34067, MC33067 http://onsemi.com 6 24 2.0 , reference output voltage change (mv) ? v ref v sat 3.2 2.4 1.6 0.8 0 0 ?50 , output saturation voltage (v) figure 8. reference output voltage change versus source current i ref , reference source current (ma) figure 9. drive output saturation voltage versus load current 0 ?1.0 ?2.0 ?3.0 3.0 i o , output load current (a) figure 10. drive output waveform 90% 10% 20 ns/div v , soft?start saturation voltage (v) figure 11. soft?start saturation voltage versus capacitor discharge current i dchg , capacitor discharge current (ma) 0 ?30 ?10 ?20 ?40 1.0 2000 1600 1200 800 400 0 f, operating frequency (khz) figure 12. operating frequency versus supply current i cc , supply current (ma) source saturation (load to ground) source saturation (load to v cc ) ol gnd t a = ?40 c t a = 25 c figure 13. supply current versus supply voltage t a = 25 c t a = ?40 c v cc , supply voltage (v) 20 12 4.0 0 i , supply current (ma) cc 16 8.0 v cc = 12 v 80 s pulsed load 120 hz rate t a = ?40 c c l = 1.0 nf t a = 25 c 0 0.2 0.4 0.6 0.8 1.0 0 20 40 60 80 100 0 2.0 4.0 6.0 8.0 10 30 40 50 60 70 80 90 0 4.0 8.0 12 16 20 v cc = 12 v c l = 1.0 nf t a = 25 c v cc = 12 v pin 10 = v ref t a = 25 c t a = ?20 c t a = ?125 c v cc = 12 v v cc t a = 25 c enable/uvlo adjust pin to v cc (dashed line) enable/uvlo adjust pin open (solid line)
mc34067, MC33067 http://onsemi.com 7 3 figure 14. mc34067 representative block diagram 12 output b 13 14 8 7 inverting input oscillator control current 16 9 8.0 v q2 r r t c t r osc c osc r vfo v ref 4.9v/3.6 v 15 v cc enable / uvlo adjust osc charge osc rc one?shot rc error amp output noninverting input soft?start ground 4 fault input power ground output a v ref d1 q1 i osc oscillator one?shot error amp clamp 3.1v error amp 9.0 a 1.0 v q q t steering flip?flop 4.2/4.0 v v ref uvlo v cc uvlo 7.0k 50k 7.0k 50k 4.9 v/3.6 v v ref 5.1 v reference 1 2 6 11 5 10 figure 15. timing diagram 5.1 v 3. 6 v c osc 5.1 v 3.6 v one?shot output a output b t os t os t os t os t os t os high state error amp output, minimum i osc current occurring at minimum input voltage, maximum load. low state error amp output, maximum i osc current occurring at maximum input voltage, minimum load. fault comparator i osc fault latch s r q
mc34067, MC33067 http://onsemi.com 8 operating description introduction as power supply designers have strived to increase power conversion efficiency and reduce passive component size, high frequency resonant mode power converters have emerged as attractive alternatives to conventional pulse?width modulated control. when compared to pulse?width modulated converters, resonant mode control offers several benefits including lower switching losses, higher efficiency, lower emi emission, and smaller size. a new integrated circuit has been developed to support this trend in power supply design. the mc34067 resonant mode controller is a high performance bipolar ic dedicated to variable frequency power control at frequencies exceeding 1.0 mhz. this integrated circuit provides the features and performance specifically for zero voltage switching resonant mode power supply applications. the primary purpose of the control chip is to provide a fixed off?time to the gates of external power mosfets at a repetition rate regulated by a feedback control loop. additional features of the ic ensure that system startup and fault conditions are administered in a safe, controlled manner. a simplified block diagram of the ic is shown on the front page, which identifies the main functional blocks and the block?to?block interconnects. figure 14 is a detailed functional diagram which accurately represents the internal circuitry. the various functions can be divided into two sections. the first section includes the primary control path which produces precise output pulses at the desired frequency. included in this section are a variable frequency oscillator, a one?shot, a pulse steering flip?flop, a pair of power mosfet drivers, and a wide bandwidth error amplifier. the second section provides several peripheral support functions including a voltage reference, undervoltage lockout, soft?start circuit, and a fault detector. primary control path the output pulse width and repetition rate are regulated through the interaction of the variable frequency oscillator, one?shot timer and error amplifier. the oscillator triggers the one?shot which generates a pulse that is alternately steered to a pair of totem pole output drivers by a toggle flip?flop. the error amplifier monitors the output of the regulator and modulates the frequency of the oscillator. high speed schottky logic is used thr oughout the primary control channel to minimi ze delays and enhance high frequency characteristics. oscillator the characteristics of the variable frequency oscillator are crucial for precise controller performance at high operating frequencies. in addition to triggering the one?shot timer and initiating the output deadtime, the oscillator also determines the initial voltage for the one?shot capacitor. the oscillator is designed to operate at frequencies exceeding 1.0 mhz. the error amplifier can control the oscillator frequency over a 1000:1 frequency range, and both the minimum and maximum frequencies are easily and accurately programmed by the proper selection of external components. the functional diagram of the oscillator and one?shot timer is shown in figure 16. the oscillator capacitor (c osc ) is initially charged by transistor q1. when c osc exceeds the 4.9 v upper threshold of the oscillator comparator, the base of q1 is pulled low allowing c osc to discharge through the external resistor, (r osc ) , and the oscillator control current, (i osc ). when the voltage on c osc falls below the 3.6 v lower threshold of the comparator, q1 turns on and again charges c osc . c osc charges from 3.6 v to 5.1 v in less than 50 ns. the high slew rate of c osc and the propagation delay of the comparator make it dif ficult to control the peak voltage. this accuracy issue is overcome by clamping the base of q1 through a diode to a voltage reference. the peak voltage of the oscillator waveform is thereby precisely set at 5.1 v. figure 16. oscillator and one?shot timer oscillator control current c osc r t c t r osc 4.9 v/3.6 v 1 2 10 3 osc charge osc rc one?shot rc d1 q1 i osc oscillator one?shot 3.1 v 4.9v/3.6v v ref error amp output 6 error amp clamp r vfo i osc v cc v cc the frequency of the oscillator is modulated by varying the current flowing out of the oscillator control current (i osc ) pin. the i osc pin is the output of a voltage regulator. the input of the voltage regulator is tied to the variable frequency oscillator. the discharge current of the oscillator increases by increasing the current out of the i osc pin. resistor r vfo is used in conjunction with the error amp output to change the i osc current. maximum frequency occurs when the error amplifier output is at its low state with a saturation voltage of 0.1 v at 1.0 ma. the minimum oscillator frequency will result when the i osc current is zero, and c osc is discharged through the external resistor (r osc ). this occurs when the error amplifier output is at its high state of 2.5 v. the minimum and maximum oscillator frequencies are programmed by the proper selection of resistor r osc and r vfo .
mc34067, MC33067 http://onsemi.com 9 the minimum frequency is programmed by r osc using equation 1: c osc where t pd is the internal propagation delay. (eq. 1) r 1 ? t pd n c t 70 ns 0.348 ? = = ? osc (min) (max) osc 5.1 3.6 the maximum oscillator frequency is set by the current through resistor r vfo . the current required to discharge c osc at the maximum oscillator frequency can be calculated by equation 2: c osc 1.5c (eq. 2) osc i 1 ? 5.1 ? 3.6 = = (max) (max) ? (max) the discharge current through r osc must also be known and can be calculated by equation 3: ? (min) c osc r osc 1.5 i 1 ? 5.1 ? 3.6 = (min) r r osc c osc r osc = r osc 1 ? ? osc (eq. 3) resistor r vfo can now be calculated by equation 4: r= vfo i (max) i r ? 2.5 ? v easat osc (eq. 4) one?shot timer the one?shot is designed to disable both outputs simultaneously providing a deadtime before either output is enabled. the one?shot capacitor (c t ) is charged concurrently with the oscillator capacitor by transistor q1, as shown in figure 16. the one?shot period begins when the oscillator comparator turns off q1, allowing c t to discharge. the period ends when resistor r t discharges c t to the threshold of the one?shot comparator. the lower threshold of the one?shot is 3.6 v. by choosing c t , r t can by solved by equation 5: 5.1 3.6 c t r t os c 0.348 = = t t t os n (eq. 5) errors in the threshold voltage and propagation delays through the output drivers will affect the one?shot period. to guarantee accuracy, the output pulse of the control chip is trimmed to within 5% of 250 ns with nominal values of r t and c t . the outputs of the oscillator and one?shot comparators are or?d together to produce the pulse t os , which drives the flip?flop and output drivers. the output pulse (t os ) is initiated by the oscillator and terminated by the one?shot comparator. with zero voltage resonant mode converters, the oscillator dischar ge time should never be set less than the one?shot period. error amplifier a fully accessible high performance error amplifier is provided for feedback control of the power supply system. the error amplifier is internally compensated and features dc open loop gain greater than 70 db, input of fset voltage of less than 10 mv and a guaranteed minimum gain?bandwidth product of 2.5 mhz. the input comm on mode ran ge extends from 1.5 v to 5.1 v, which includes the reference voltage. figure 17. error amplifier and clamp r vfo oscillator control current 3.1 v error amp output noninverting input inverting input error amp i osc 7 8 6 3 error amp clamp when the error amplifier output is coupled to the i osc pin by r vfo , as illustrated in figure 17, it provides the oscillator control current, i osc . the output swing of the error amplifier is restricted by a clamp circuit to improve its transient recovery time. output section the pulse(t os ), generated by the oscillator and one?shot timer is gated to dual totem?pole output drives by the steering flip?flop shown in figure 18. positive transitions of t os toggle the flip?flop, which causes the pulses to alternate between output a and output b. the flip?flop is reset by the undervoltage lockout circuit during startup to guarantee that the first pulse appears at output a. figure 18. steering flip?flop and output drivers output a r 12 13 14 output b power ground q q t steering flip?flop pwr gnd v cc v cc pwr gnd
mc34067, MC33067 http://onsemi.com 10 the totem?pole output drivers are ideally suited for driving power mosfets and are capable of sourcing and sinking 1.5 a. rise and fall times are typically 20 ns and 15 ns respectfully when dr iving a 1.0 nf load. high source/sink capability in a totem?pole driver normally increases the risk of high cross conduction current during output transitions. the mc34067 utilizes a unique design that virtually eliminates cross conduction, thus controlling the chip power dissipation at high frequencies. a separate power ground pin is provided to isolate the sensitive analog circuitry from large transient currents. figure 19. undervoltage lockout and reference 8.0 v v ref 15 9 v cc 5 v ref 4.2/4.0 v v ref uvlo v cc uvlo 7.0k 50k 7.0k 50k 5.1 v reference enable / uvlo adjust uvlo peripheral support functions the mc34067 resonant controller provides a number of support and protection functions including a precision voltage reference, undervoltage lockout comparators, soft?start circuitry, and a fault detector. these peripheral circuits ensure that the power supply can be turned on and off in a controlled manner and that the system will be quickly disabled when a fault condition occurs. undervoltage lockout and voltage reference separate undervoltage lockout comparators sense the input v cc voltage and the regulated reference voltage as illustrated in figure 19. when v cc increases to the upper threshold voltage, the v cc uvlo comparator enables the reference regulator. after the v ref output of the reference regulator rises to 4.2 v, the v ref uvlo comparator switches the uvlo signal to a logic zero state enabling the primary control path. reducing v cc to the lower threshold voltage causes the v cc uvlo comparator to disable the reference regulator. the v ref uvlo comparator then switches the uvlo output to a logic one state disabling the controller. the enable/uvlo adjust pin allows the power supply designer to select the v cc uvlo threshold voltages. when this pin is open, the comparator switches the controller on at 16 v and off at 9.0 v. if this pin is connected to the v cc terminal, the upper and lowe r thresholds are reduced to 9.0 v and 8.6 v, respectively. forcing the enable/uvlo adjust pin low will pull the v cc uvlo comparator input low (through an internal diode) turning off the controller. the reference regulator provides a precise 5.1 v reference to internal circuitry and can deliver up to 10 ma to external loads. the reference is trimmed to better than 2% initial accuracy and includes active short circuit protection. fault detection converter protection from adverse operating conditions can be implemented with proper use of the fault comparator and latch blocks that are illustrated in figure 20. the fault comparator has an input threshold of 1.0 v and when exceeded, sets the fault latch and generates two logic signals that simultaneously disable the primary control path. the signal line labeled ?fault? connects directly to two gates that control the output drivers. this direct path reduces the driver turn?off propagation delay to approximately 70 ns. the fault latch output is or?ed with the uvlo output that is derived from the v ref uvlo comparator, to produce the logic output labeled ?uvlo+fault?. this signal disables the oscillator and the one?shot by forcing both the c osc and c t capacitors to be continually charged. the fault latch is automatically reset during startup by a logic ?1? that appears at the v ref uvlo comparator output. the latch can also be reset after startup by momentarily pulling the enable/uvlo adjust pin low to disable the reference. note that after activation, the fault latch will remain in a set state only as long as v cc is provided to the mc34067. also, drive output b will assume a high state if the fault input signal drops below the 1.0 v threshold level even after the fault latch has been set. in some applications this characteristic could be problematic but it can be easily remedied by ac coupling drive output b.
mc34067, MC33067 http://onsemi.com 11 fault latch s r q figure 20. fault detector and soft?start c soft?start fault input 10 9.0 a 1.0 v 11 6 ground soft?start buffer error amp clamp uvlo + fault uvlo fault comparator fault soft?start circuit the soft?start circuit shown in figure 20 forces the variable frequency oscillator to start at the maximum frequency and ramp downward until regulated by the feedback control loop. the external capacitor at the c soft?start terminal is initially discharged by the uvlo+fault signal. the low voltage on the capacitor passes through the soft?start buffer to hold the error amplifier output low. after uvlo+fault switches to a logic zero, the soft?start capacitor is charged by a 9.0 a current source. the buffer allows the error amplifier output to follow the soft?start capacitor until it is regulated by the error amplifier inputs. the soft?start function is generally applicable to controllers operating below resonance and can be disabled by simply opening the c soft?start terminal. applications information the mc34067 is specifically designed for zero voltage switching (zvs) quasi?resonant converter (qrc) applications. the ic is optimized for double?ended push?pull or bridge type converters operating in continuous conduction mode. operation of this type of zvs with resonant properties is similar to standard push?pull or bridge circuits in that the energy is transferred during the transistor on?time. the difference is that a series resonant tank is usually introduced to shape the voltage across the power transistor prior to turn?on. the resonant tank in this topology is not used to deliver energy to the output as is the case with zero current switch topologies. when the power transistor is enabled the voltage across it should already be zero, yielding minimal switching loss. figure 21 shows a timing diagram for a half?bridge zvs qrc. an application circuit is shown in figure 22. the circuit built is a dc to dc half?bridge converter delivering 75 w to the output from a 48 v source. when building a zero voltage switch (zvs) circuit, the objective is to waveshape the power transistor?s voltage waveform so that the voltage across the transistor is zero when the device is turned on. the purpose of the control ic is to allow a resonant tank to waveshape the voltage across the power transistor while still maintaining regulation. this is accomplished by maintaining a fixed deadtime and by varying the frequency; thus the effective duty cycle is changed. primary side resonance can be used with zvs circuits. in the application circuit, the elements that make the resonant tank are the primary leakage inductance of the transformer (l l ) and the average output capacitance (c oss ) of a power mosfet (c r ). the desired resonant frequency for the application circuit is calculated by equation 6: l l 2c r 1 = 2 ? r (eq. 6) in the application circuit, the operating voltage is low and the value of c oss versus drain voltage is known. because the c oss of a mosfet changes with drain voltage, the value of the c r is approximated as the average c oss of the mosfet. for the application circuit the average c oss can be calculated by equation 7: measured at c r 1 2 2 * c oss = in v (eq. 7) the mosfet chosen fixes c r and that l l is adjusted to achieve the desired resonant frequency. however, the desired resonant frequency is less critical than the leakage inductance. figure 21 shows the primary current ramping toward its peak value during the resonant transition. during this time, there is circulating current flowing through the secondary inductance, which effectively makes the primary inductance appear shorted. therefore, the current through the primary will ramp to its peak value at a rate controlled by the leakage inductance and the applied voltage. energy is not transferred to the secondary during this stage, because the primary current has not overcome the circulating current in the secondary. the larger the leakage inductance, the longer it takes for the primary current to slew. the practical effect of this is to lower the duty cycle, thus reducing the operating range.
mc34067, MC33067 http://onsemi.com 12 the maximum duty cycle is controlled by the leakage inductance, not by the mc34067. the one?shot in the mc34067 only assures that the power switch is turned on under a zero voltage condition. adjust the one?shot period so that the output switch is activated while the primary current is slewing but before the current changes polarity. the resonant stage should then be designed to be as long as the time for the primary current to go to 0 a. figure 21. application timing diagram 0 a + i primary ? i primary output rectifier voltage 0 v 1/2 v in v in drive output b drive output a one?shot 3.6 v 5.1 v c osc 3.6 v 5.1 v v in /turns ratio primary current input voltage
mc34067, MC33067 http://onsemi.com 13 inductance = 1.8 h mbr2535 330pf 100pf 16k 1.6k 330pf 1500pf 220pf 0.01 10k 1.1k 2.7k 18k 10 v cc 15 9 1 2 16 3 6 8 7 11 4 reference 5 14 13 12 10 470pf 470 3.9k 1n5819 t2 mtp33n10e 100 1.0 1.0 t3 1.0k 1.0k 100 1n5819 x 4 v in 500pf 51/0.5w ctl 2 30 v out l1 l2 figure 22. application circuit line regulation load regulation output ripple efficiency test conditions results v in = 40 v to 56 v, i o =15 a v in = 48 v, i o = 10 a to 15 a v in o = 48 v, i = 15 a, f 20 mv = switch = 1.0 mhz v in o = 48 v, i = 10 a, f switch = 1.7 mhz v in o = 48 v, i = 15 a, f switch = 1.0 mhz 0.198% 4.0 mv = 0.039% 25 mv p?p 83.5% 84.2% t1 = primary: 12 turns #48 awg (1300 strands litz wire) secondary: 6 turns center tapped #48 awg (1300 strands litz wire) core: philips 3f3 4312 020 4124 bobbin: philips 4322 021 3525 primary leakage inductance = 1.0 h t2 = all windings: 8 turns #36 awg core: philips 3f3 ep7?3f3 bobbin: philips ep7pcb1?6 t3 = coilcraft d1870 (100 turns) l1 = 2 turns #48 awg (1300 strands litz wire) core: philips 3f3 ep10?3f3 bobbin: philips ep10pcb1?8 l2 = 5 turns #48 awg (1300 strands litz wire) core: 0.5 inductance = 100 nh diameter air code heatsinks = aavid engineering inc. 533402b02552 with clip mc34067?5803 insulators = berquist sil?pad 1500 5.0 v 36 v to 56 v t1 1n5819 500pf 51/0.5w
mc34067, MC33067 http://onsemi.com 14 5.0 (bottom view) figure 23. printed circuit board and component layout (top view) 3.875
mc34067, MC33067 http://onsemi.com 15 package dimensions pdip?16 p suffix case 648?08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic?16w dw suffix case 751g?03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7
mc34067, MC33067 http://onsemi.com 16 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc34067/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

▲Up To Search▲

Price & Availability of MC33067

	To Download MC33067 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .